pdf文档 FPGA可编程逻辑器件芯片5AGXBB3D4F31C4N中文规格书

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摘要:找FPGA和CPLD可编程逻辑器件,上深圳宇航军工半导体有限公司ThePLLsintheArriaVdevicessupportthefollowingfeatures:••••••••••FrequencysynthesisOn-chipclockdeskewJitterattenuationCounterreconfigurationProgrammableoutputclockdutycyclesPLLcascadingReferenceclockswitchoverProgrammablebandwidthDynamicphaseshiftZerodelaybuffersFractionalPLLInadditiontointegerPLLs,theArriaVdevicesuseafractionalPLLarchitecture.Thedeviceshaveupto16PLLs,eachwith18outputcounters.OnefractionalPLLcanuseupto18outputcountersandtwoadjacentfractionalPLLssharethe18outputcounters.YoucanusetheoutputcounterstoreducePLLusageintwoways:•ReducethenumberofoscillatorsthatarerequiredonyourboardbyusingfractionalPLLs•Reducethenumberofclockpinsthatareusedi

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